Projects

PLANNED DIRECTIONS4 ENTRIES

1. 01

   Workload characterization for AI data movement

   What a real model execution reads and writes, how often, and from where — in a trace format the modeling work below can consume directly.

   • workload analysis
   • traces
   • data movement

   in design
2. 02

   Memory system and HBM modeling

   Bandwidth, latency and bank-level behaviour under those traces. How much of an accelerator stall is actually a memory-system property?

   • memory systems
   • HBM
   • performance modeling

   in design
3. 03

   NoC / interconnect simulation

   Topology, routing and flow control driven by the same traffic instead of synthetic uniform-random.

   • NoC
   • interconnect
   • simulation

   in design
4. 04

   RTL network datapath

   A synthesizable block with its own testbench, taking one of the results above from model to hardware.

   • RTL
   • SystemVerilog
   • verification

   in design