About
AI DATA MOVEMENT · MEMORY SYSTEMS · INTERCONNECT · RTL
I am Shengyi Wei, a digital design and computer architecture engineer. My work sits around AI data movement: memory systems, interconnects and network-on-chip, workload-driven performance modeling, simulation, and RTL.
From the hardware's side, an inference run is a traffic pattern. I work on reading that pattern off real workloads, and on what follows from it: memory systems, on-chip and chip-to-chip networks, and the RTL underneath.
That means starting from what a model actually does to memory rather than from a block diagram, and carrying the measurement forward into the memory system, the interconnect, and then the hardware it justifies.
Projects is what I am building. Notes is English write-ups. Reading is notes worked through from other people's material — a blog series, a specification, a repository — on PCIe, ASIC synthesis, RTL coding style and GPU microarchitecture, with the source named on every entry. Those bodies are still Chinese, and are being rewritten.